The present invention relates generally to the field of integrated circuit design, and, more specifically, to the field of logic synthesis of electronic circuit designs. Yet more specifically, the present invention relates to a method, system, and computer program product for optimizing logic during synthesis of logic designs.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. The process of converting the functional specifications of an electronic circuit into a layout is called the physical design.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
In trying to improve a logic design during synthesis, it is important to fix the most critical timing path. Therefore, synthesis tools first attempt to optimize the logic in the timing path having the worst timing problem. Once the timing through this timing path is improved, the tool then attempts to fix the next worst timing problem.
A timing path is defined as being the path between an input and an output, an input and a latch, a latch and an output, and a first latch and a second latch. The logic in the timing path having the worst timing problem is selected to be optimized.
The latches in the logic may be implemented using transparent latches. For transparent latches, the data appearing on the input side of the transparent latch flushes through to the output side of the latch while the clock is on.
The synthesis tool uses one or both of two approaches to fix the timing problem. One approach is to reduce the amount of logic, and the other approach is to go through the existing logic faster. Neither of these approaches recognize the special situation of the transparent latch, where it is possible to start the signal into the logic sooner by getting it to the input of the transparent latch sooner.
Therefore, a need exists for a method, system, and product for optimizing logic during synthesis of logic designs by selecting logic in multiple timing paths when the timing path having the worst timing problem includes a transparent latch as its input node.
A method, system, and computer program product are disclosed for optimizing logic during synthesis of a logic design. A first timing path within the logic design is identified. The first timing path has first logic to be optimized in order to improve timing in the first timing path. A determination is then made regarding whether an input node to the first timing path is a particular device. In response to the input node being the particular device, a determination is made regarding whether optimizing second logic included in a second timing path having the particular device as its output node will improve timing in the first timing path. In response to a determination that optimizing the second logic will improve timing in the first timing path, both the second logic and the first logic are selected to be optimized.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.